The present invention relates to testing the correct operation of integrated circuits; more particularly, the present invention relates to testing an input/output circuit in an integrated circuit.
Before an integrated circuit (IC) may be used in an application, it is typically necessary to verify the proper functionality and timing of components within each input/output (I/O) circuit of the IC. Verifying the functionality of an IC is typically accomplished by placing the IC on a tester that includes a tester channel for each I/O pin on the IC. Subsequently, each I/O buffer coupled to an I/O pin is tested for functionality, timing, performance, etc. However, there are often problems associated with testing an IC in this manner. One problem is that testing each I/O pin on an IC is time consuming and often expensive due to test equipment costs. Another problem is that the speed of the test equipment is typically not fast enough to keep pace with the IC. Moreover, existing test equipment is not capable of testing high-speed source synchronous systems.
In order to solve the problems of exclusively using a tester to test an IC, several contemporary testing schemes use the IC to assist in the testing. This process is commonly referred to as an I/O loopback test. I/O loopback tests are typically carried out by providing data from a functional logic block (or FLB) within the IC (e.g., a microprocessor), and driving the data out through the output component of each I/O buffer. Subsequently, the data is driven back through the input component of the I/O buffer to the FLB in order to verify to that the correct data has been received. Consequently, the IC verifies whether the input and output components of each I/O buffer is functioning properly.
The problem with conventional I/O loopback tests, however, is that generating and verifying test data patterns at the FLB require the addition of special logic within the FLB. Further, since the FLB is required to generate and check data, it is not possible to conduct other tests within the IC (e.g., the effect of I/O data on the FLB or vice versa). Therefore, a method and apparatus for performing an I/O loopback test without using core logic within a FLB is desired.
An integrated circuit including a plurality of input/output (I/O) buffers is disclosed. In one embodiment, the integrated circuit contains a first I/O buffer that includes a first I/O pad, a first output driver coupled to the first I/O pad and a first input receiver coupled to the first I/O pad. In addition, the first I/O buffer includes a first I/O test circuit coupled to the first output driver and the first input receiver, wherein the first I/O test circuit generates test pattern signals whenever the first I/O test circuit is operating in a test mode.